drivers/usb/cdns3

Cadence USBSS (CDNS3) dual-role USB 3.x controller

Cadence's licensable USB 3.x controller IP that handles both host and device (dual-role) duties on systems-on-chip. It is integrated into shipping embedded platforms including NXP's i.MX 8 family, Texas Instruments' Jacinto/K3 J721E processors, and StarFive's RISC-V SoCs, where it drives the USB-C and USB 3.0 ports.

keep conf=0.94 deploy=medium replacement=none subsystem=usb category=bus-usb
94%

recommendation

It should stay because the underlying Cadence USB3 controller IP is still actively sold and is built into current SoCs from NXP, TI, and StarFive that ship in 2025. The code is being maintained, with real bug fixes landing in upstream Linux through 2025-2026, and there is no replacement driver available since the Cadence-specific core and SoC glue are required even though the host path itself hands off to xHCI.

repository signals

29 files
19,307 source lines
128 commits, 5y
+1,580 / −1,018 lines added / removed, 5y
51 authors, 5y
monthly commits · 2021-04-21 → 2026-04-21 · 128 total · active in 46/61 months
2021 2022 2023 2024 2025 2026 2021-04: 3 commits · +11 −9 2021-05: 12 commits · +39 −40 2021-06: 6 commits · +14 −17 2021-07: 0 commits · +0 −0 2021-08: 1 commit · +1 −1 2021-09: 2 commits · +17 −3 2021-10: 0 commits · +0 −0 2021-11: 3 commits · +8 −17 2021-12: 6 commits · +33 −9 2022-01: 3 commits · +157 −157 2022-02: 0 commits · +0 −0 2022-03: 1 commit · +5 −2 2022-04: 0 commits · +0 −0 2022-05: 1 commit · +49 −7 2022-06: 3 commits · +13 −10 2022-07: 1 commit · +6 −3 2022-08: 3 commits · +11 −5 2022-09: 1 commit · +0 −2 2022-10: 2 commits · +31 −33 2022-11: 4 commits · +60 −23 2022-12: 1 commit · +63 −53 2023-01: 0 commits · +0 −0 2023-02: 2 commits · +15 −33 2023-03: 4 commits · +18 −36 2023-04: 0 commits · +0 −0 2023-05: 10 commits · +304 −25 2023-06: 2 commits · +20 −10 2023-07: 5 commits · +16 −5 2023-08: 0 commits · +0 −0 2023-09: 1 commit · +1 −2 2023-10: 2 commits · +5 −40 2023-11: 2 commits · +180 −177 2023-12: 5 commits · +122 −41 2024-01: 0 commits · +0 −0 2024-02: 5 commits · +35 −11 2024-03: 0 commits · +0 −0 2024-04: 0 commits · +0 −0 2024-05: 4 commits · +46 −21 2024-06: 0 commits · +0 −0 2024-07: 0 commits · +0 −0 2024-08: 2 commits · +32 −1 2024-09: 4 commits · +28 −24 2024-10: 0 commits · +0 −0 2024-11: 1 commit · +11 −19 2024-12: 1 commit · +1 −3 2025-01: 1 commit · +7 −6 2025-02: 5 commits · +87 −44 2025-03: 2 commits · +2 −2 2025-04: 2 commits · +52 −3 2025-05: 2 commits · +23 −2 2025-06: 2 commits · +29 −7 2025-07: 0 commits · +0 −0 2025-08: 2 commits · +0 −86 2025-09: 2 commits · +7 −6 2025-10: 1 commit · +1 −4 2025-11: 1 commit · +0 −2 2025-12: 0 commits · +0 −0 2026-01: 1 commit · +1 −1 2026-02: 2 commits · +15 −16 2026-03: 1 commit · +3 −0 2026-04: 1 commit · +1 −0

sources

  1. git.kernel.org

    Upstream history for drivers/usb/cdns3 shows continuing fixes into 2025-2026 rather than abandonment or removal.

  2. cadence.com

    Cadence still markets the USB3 controller IP, indicating the core hardware family is not obsolete.

  3. nxp.com

    NXP lists the i.MX 8QuadXPlus MEK as Active, supporting ongoing availability of an SoC family using this driver.

  4. software-dl.ti.com

    TI documents CDNS3 integration on J721E and its EVM dual-role USB port, showing current deployment on shipping embedded platforms.

  5. cateee.net

    LKDDb shows CONFIG_USB_CDNS3_IMX present through current kernel heads, with matching i.MX8 USB3 device IDs.

codex reasoning notes (technical)

Keep. Local shell inspection of Kconfig and source shows an active Cadence dual-role USB controller driver with platform glue for NXP i.MX, TI K3/J721E, and StarFive. Local shell git log on the directory shows multiple real bug fixes in 2025-2026 and no evident removal/deprecation trend; the kernel.org log URL is cited as the canonical stable page corresponding to that shell-derived history. Vendor/deployment evidence came from web search results: Cadence product page, NXP active MEK page, TI SDK CDNS3 documentation, and LKDDb. No natural upstream replacement exists for the same Cadence DRD hardware; host mode already delegates to xHCI, but the cdns3 glue/core remains necessary.