Xilinx AXI4-Stream FIFO character interface
A character-device interface to the AMD/Xilinx AXI4-Stream FIFO LogiCORE IP block, a building block embedded in FPGA designs (Zynq, Versal, and similar Xilinx parts) that lets software push and pull packets to AXI-Stream peripherals such as AXI Ethernet without needing a DMA engine. It is mostly used in custom FPGA and industrial designs.
recommendation
Worth keeping but documenting its niche. The underlying Xilinx IP is still a current AMD product (PG080 was refreshed in early 2026) and the driver continues to see real review traffic on the linux-staging list, including patches reviewed by Greg Kroah-Hartman and Ovidiu Panait. It serves a small but real audience of FPGA and industrial integrators, and although it has lingered in staging, there are no signs of removal — just ongoing cleanup toward eventual promotion.
repository signals
sources
- docs.amd.com
AMD product guide PG080 for AXI4-Stream FIFO v4.3 was updated on 2026-01-09, indicating the IP core remains a current AMD/Xilinx offering rather than an obsolete legacy block.
- spinics.net
A February 9, 2026 patch series targeted this driver for probe-logic cleanup, showing active upstream maintenance rather than abandonment or removal planning.
- spinics.net
The v8 review thread includes maintainer/author engagement from Ovidiu Panait on February 9, 2026, another sign of ongoing stewardship.
- spinics.net
A March 1, 2026 patch removed unnecessary variable initializations in axis-fifo.c, confirming recent substantive code traffic.
- spinics.net
Greg KH replied on March 30, 2026 to an axis-fifo patch, showing the driver is still on the active staging review path and not under visible removal discussion.
- cateee.net
LKDDb shows CONFIG_XIL_AXIS_FIFO still present through 7.0-rc+HEAD and maps it to Xilinx AXI FIFO compatible strings xlnx,axi-fifo-mm-s-4.1/4.2/4.3.
codex reasoning notes (technical)
Local `exec_command` inspection of `drivers/staging/axis-fifo` shows a real OF platform misc-char driver for Xilinx AXI-Stream FIFO IP (`xlnx,axi-fifo-mm-s-*`) used as a memory-mapped interface to AXI Stream / AXI Ethernet without DMA. External URLs were obtained via `web.search_query`: AMD PG080 establishes the IP is still current in 2026, Spinics threads show active 2026 cleanup/review traffic and no removal series, and LKDDb confirms the config remains in current kernels. Because the hardware/IP is still sold and upstream attention is active but the driver remains staging and likely serves niche FPGA/industrial deployments, `keep-annotate` fits better than deprecate/remove.