Internal resource-configuration code for AMD's Display Core Next 3.5.1 hardware block, used inside the amdgpu display pipeline to describe pipes, planes, and clocks for recent AMD integrated GPUs (Ryzen APUs in the Strix/Hawk Point generation). It is part of the larger amdgpu DRM driver, not a standalone driver itself.
This is not actually a driver directory; it is one of many per-ASIC resource subfolders within AMD's display-core code that the amdgpu DRM driver pulls in to support the DCN 3.5.1 display block. It only makes sense as part of the larger AMD GPU driver and cannot be evaluated for keep-or-remove on its own.
repository signals
2files
2,259source lines
49commits, 5y
+2,411 / −152lines added / removed, 5y
31authors, 5y
monthly commits · 2021-04-21 → 2026-04-21 · 49 total · active in 21/61 months
sources
No sources cited.
codex reasoning notes (technical)
Not a driver directory: DCN3.5.1 display resource subdirectory inside the AMD DRM stack, containing internal display-core resource code rather than a kernel-bound hardware driver entry point.