Internal display-pipeline plumbing inside AMD's Display Core, specifically the MPC (Multiple Pipe/Plane Combiner) layer for the first-generation DCN1.0 hardware shipped in Raven Ridge Ryzen APUs around 2017-2018. It composes and blends display planes before they reach the output and is consumed by the broader amdgpu graphics driver.
This is not actually a driver directory; it is a set of internal helper files for the Multiple Pipe/Plane Combiner block within AMD's Display Core code, used by the amdgpu graphics driver to drive the DCN1.0 display hardware found in Raven Ridge era APUs. It only exists as a building block of the larger amdgpu driver and is not loaded or removed independently.
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monthly commits · 2021-04-21 → 2026-04-21 · 2 total · active in 2/61 months
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codex reasoning notes (technical)
Not a driver directory: internal AMD Display Core/DCN10 display-pipeline helper code within amdgpu, not a standalone kernel-bound hardware driver.