Internal helper code inside AMD's Display Core that programs the DCN 3.5 generation display engine, which is integrated into AMD's recent APUs such as the Ryzen "Phoenix" and "Hawk Point" mobile processors. It handles low-level sequencing of the display pipeline (power gating, clock and pipe setup) on behalf of the broader amdgpu graphics driver.
This is not actually a driver directory; it is an internal subcomponent of the amdgpu Display Core (DC) stack containing the hardware sequencer routines specific to the DCN 3.5 display block found in recent AMD APUs. It is built as part of the larger amdgpu driver rather than as a standalone module, so it has no independent lifecycle to evaluate.
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90commits, 5y
+2,617 / −504lines added / removed, 5y
45authors, 5y
monthly commits · 2021-04-21 → 2026-04-21 · 90 total · active in 29/61 months
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codex reasoning notes (technical)
Not a driver directory: DCN3.5 display HW sequencer support code under amdgpu DC, an internal helper subdirectory rather than a standalone kernel-bound hardware driver.