drivers/gpu/drm/amd/display/dc/hwss/dcn10

AMD DCN1.0 Display Hardware Sequencer Helpers

Internal helper code within AMD's amdgpu display stack that programs the DCN1.0 display pipeline — the display hardware first introduced in 2017 with Raven Ridge Ryzen APUs (e.g. Ryzen 5 2400G). It handles the low-level sequencing of pipes, planes, and timing for that generation's display controller.

not-a-driver conf=1.00 deploy=none replacement=none subsystem=gpu category=not-a-driver

100%

recommendation

This is not a standalone driver but an internal subdirectory of the amdgpu display code stack (DC). It contains the hardware-sequencer logic for the first generation of AMD's Display Core Next (DCN1.0) display engine, used inside Raven Ridge / Ryzen APUs. It ships as part of amdgpu and has no independent lifecycle.

repository signals

4 files

4,534 source lines

65 commits, 5y

+4,825 / −291 lines added / removed, 5y

37 authors, 5y

monthly commits · 2021-04-21 → 2026-04-21 · 65 total · active in 25/61 months

sources

No sources cited.

codex reasoning notes (technical)

Not a driver directory: AMD DCN10 hardware-sequencer implementation under the amdgpu display stack, i.e. internal display helper code rather than a standalone kernel-bound hardware driver.